In a memory architecture with a uniform or unified memory access, sometimes referred to as a unified memory architecture (UMA), a processor and a graphic controller share system memory to lower costs. Typically, a UMA memory architecture may be optimized to handle memory requests (read/write accesses) from the processor into the system memory. The typical UMA memory architecture compromises the memory requests made by the graphics controller. Today, graphics performance has become more important to support three dimensions (3D) as well as higher resolution.
In the typical UMA memory architecture, cache memory uses a fixed sixty four (64) byte cache-line to support memory requests made by both the processor and memory requests made by the graphics controller. A typical memory controller in a UMA memory architecture has one or two memory channels. Each memory channel shares all address lines in an address bus with each memory module in order to perform read or write accesses. The data bus in the typical memory channel is typically sixty-four (64) bits wide so that eight (8) bytes of contiguous data for a given address are accessed from memory at the same time. The bits of the data bus may be routed to memory modules in different ways depending upon the type of memory and memory size utilized.
While a processor typically uses all 64 bits of contiguous data accessed from the memory, a graphics controller typically may not. Much of the contiguous data may be discarded when a graphics controller makes a memory request in a UMA memory architecture. Thus, the bandwidth of the memory channel may be inefficiently used by memory requests issued by the graphics controller in the typical UMA memory architecture.
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